Many semiconductor devices, such as microprocessors or “memory semiconductor dies” used as an example herein, include a core memory array, which comprise bitlines that run in a direction perpendicular to wordlines. The memory semiconductor die also includes sense amplifiers, which are typically situated near the center of the semiconductor die, and VCC and VSS pads, which may be situated at the top or bottom of the semiconductor die. The VCC and VSS pads can be coupled to the sense amplifiers by power interconnect lines, which are typically formed over the core memory array in an interconnect metal layer in the semiconductor die.
In a conventional memory semiconductor die, the power interconnect lines generally run straight lines over the bitlines. However, the bitlines are substantially narrower than the power interconnect lines and the spacing between adjacent bitlines is substantially less than the spacing between adjacent power interconnect lines. As a result, some of the bitlines may be situated under power interconnect lines, while other bitlines may not be situated under power interconnect lines. As a consequence, the coupling capacitance between a bitline situated under a power interconnect line and the power interconnect line will be greater than the coupling capacitance for a bitline that is not situated under the power interconnect line.
Thus, an unbalanced coupling capacitance between bitlines in a memory core array and power interconnect lines situated above the memory core array can exist in a conventional memory semiconductor die. However, for effective bitline sensing, it is advantageous to have a balanced coupling capacitance between bitlines and power interconnect lines.
Thus, there is a need in the art for balanced coupling capacitance between bitlines in a memory core array and power interconnect lines situated over the memory core array.